FIG. 1 (Prior Art) is a simplified cross-sectional diagram of a conventional planar double diffused field effect transistor. A layer of N type epitaxial silicon 1 is formed on an N+ type substrate 2. A P body region 3A and a P+ body region are formed into the epitaxial layer from upper surface 4, and an N+ type source region 5 is formed into the body regions 3A and 3B from upper surface 4. To turn the transistor on (i.e., make it conductive), a positive potential is placed on gate 6. The positive potential on gate 6 causes what is called a channel region to form in the surface portion of P body region 3A underneath the gate and also causes what is called an accumulation region to form in the surface portion of the N type epitaxial silicon region 1A immediately underneath the gate. Electrons can then flow as generally indicated by the arrow from the N+ type source region 5, through the channel region in P body region 3A, through the accumulation region of N type epitaxial layer 1A, downward through the N type epitaxial region 1A, downward through the N+ type substrate 2, and to a drain electrode 7. If gate 6 does not have a positive potential, then no channel is formed and no electron flow from source to drain takes place. The transistor is therefore turned off (i.e., nonconductive).
FIG. 2 (Prior Art) is a simplified cross-sectional diagram of another type of double diffused field effect transistor, a trench field effect transistor. An N type epitaxial layer 1 is formed on a N+ type substrate 2. Body regions 3A and 3B and N+ type source region 5 are then formed in similar double diffused fashion to the body and source regions in the planar transistor. In the case of the trench transistor, a trench is etched down into epitaxial layer 1 from upper surface 4. A gate oxide layer 8 is then grown in this trench on the side walls and the trench bottom. An amount of polysilicon or other suitable material is then deposited on the gate oxide in the trench to form a gate 9. For additional information on trench field effect transistors, see U.S. Pat. No. 5,072,266 entitled "Trench DMOS Power Transistor With Field-Shaping Body Profile And Three-Dimensional Geometry", the subject matter of which is incorporated herein by reference.
To turn the trench transistor on, a positive potential is placed on gate 9. The positive potential causes a channel region to form in the portion of the P body region 3A which forms part of the sidewall of the trench and causes an accumulation region to form in the portion of the N type epitaxial layer region 1A which forms a part of the sidewall of the trench. Electrons can then flow as indicated by the arrow from the N+ type source region 5, downward through the channel region of P body region 3A, downward through the accumulation region, downward through the remainder of the N type epitaxial region 1A, downward through the N+ type substrate 2, and to a drain electrode 7. If gate 9 does not have a positive potential, then no channel is formed and no electron flow from source to drain takes place. The transistor is therefore turned off.
It is desirable that such transistors have low source-to-drain resistances R.sub.DSon when turned on. As depicted pictorially in FIG. 1, the resistance R.sub.DSon in the planar structure is made up of the resistance R.sub.CH through the channel, the resistance R.sub.ACC laterally through the accumulation region, the resistance R.sub.JFET vertically through the pinched portion of the N type epitaxial region 1A between the two adjacent P body regions, the resistance R.sub.DRIFT vertically through the remainder of the N type epitaxial region 1A to the substrate, and the resistance R.sub.SUB vertically through the substrate to the drain electrode. As depicted pictorially in FIG. 2, the resistance R.sub.DSon in the trench structure is made up of the resistance R.sub.CH vertically through the channel, the resistance R.sub.ACC vertically through the accumulation region, the resistance R.sub.DRIFT vertically through the remainder of the N type epitaxial region 1A, and the resistance R.sub.SUB vertically through the substrate to the drain electrode. Note that R.sub.JFET is eliminated in the trench device. Because the conductivity of silicon increases with dopant concentration, epitaxial silicon layer 1 is relatively heavily doped to reduce the R.sub.DRIFT and thereby reduce R.sub.DSon.
It is also desirable that such transistors not suffer what is called "punchthrough". When a high voltage is placed across the transistor from the source to the drain such as when the transistor is off in a high voltage application, a depletion region will form along the N+ type source to P body junction. Similarly, a depletion region will form along the P body to N type epitaxial layer region junction. If the source-to-drain voltage is high enough, the depletion regions will extend so far inward into the P body region 3A that they will meet. This is called punchthrough. As a result, an undesirable conductive path is formed through the P body region 3A when the transistor should be off.
A power field effect transistor is sought which has both low R.sub.DSon as well as the ability to withstand high source-to-drain voltages without suffering punchthrough problems.